1. Field of Invention
The present invention relates to a method of manufacturing the capacitor of a dynamic random access memory (DRAM). More particularly, the present invention relates to a method of manufacturing a deep trench capacitor.
2. Description of Related Art
With advances made in semiconductors regarding deep sub-micron manufacturing technique, dimensions of devices have reduced correspondingly. With size reduction, space for accommodating a capacitor in a dynamic random access memory (DRAM) unit is also reduced. However, the storage capacity of a computer must increase due to a general increase in size of software programs. Such conflicting demands indicate the need for a change in the manufacturing method of DRAM.
DRAM capacitors can be roughly divided into two major types, a stacked capacitor or a deep trench capacitor. Yet, both types of capacitors face similar technical problems in manufacturing as dimension of constituent semiconductor devices in a silicon chip is reduced
Most conventional semiconductor capacitors have a stacked type structure. At present, major methods for increasing effective surface area of a stacked capacitor includes depositing hemispherical grains (HSG) and shaping the capacitor surfaces into crown, fin, cylinder or extended structures. Although the stacked capacitor enjoys much popularity, planarization is still a big fabrication issue demanding much attention especially when size of each memory device is reduced by miniaturization.
Because a deep trench capacitor is formed inside a substrate, planarization is not a problem. In fact, the deep trench structure facilitates the fabrication of small memory devices. However, producing semiconductor devices having a line width of about 0.2 xcexcm demands the production of a trench having an aspect ratio of up to 35:1. To advance to the production of device with a line width of 0.17 xcexcm or less, even less space is available for housing each trench and hence the difficulties in shaping a deep trench by photolithographic and etching processes are deeply intensified. Furthermore, gap-filling materials necessary for filling the deep trench must be improved.
Nevertheless, for 0.17 xcexcm line width generation of deep trench DRAM capacitors, one major factor that determines the failure of a single memory cell is whether the interface between a first conductive layer and a second conductive layer inside the deep trench structure is conductive or not. Hence, how to maintain conduction at the interface between the first and second conductive layer inside the trench is of major importance.
FIGS. 1A through 1D are schematic cross-sectional views showing the progression of steps for fabricating a conventional deep trench type capacitor. As shown in FIG. 1A, a patterned mask layer 102 is formed over a substrate 100. The mask layer 102 and the substrate 100 are sequentially etched to form a deep trench 104. A doped region 106 is formed at the bottom of the deep trench 104 to serve as a storage electrode of the subsequently formed deep trench capacitor.
As shown in FIG. 1B, a conformal dielectric layer 108 is formed over the exposed surface of the deep trench 104. A chemical vapor deposition is conducted to fill up the deep trench 104 and form a conductive layer 110. The conductive layer 110 can be a doped polysilicon layer, for example. Because the gap-filling capacity of polysilicon deteriorates as critical dimensions of the deep trench 104 are reduced, a seam 112 is formed in the innermost portion of the conductive layer 110.
As shown in FIG. 1C, a portion of the conductive layer 110 at the top of the deep trench 104 is removed to form a conductive layer 110a at the bottom of the deep trench 104. Meanwhile, the dielectric layer 108 at the top end of the deep trench 104 is also removed. When the layer of conductive material near the top is removed, the seam 112 is exposed A collar oxide layer 114 conformal to the exposed surface is formed over the substrate 100 so that the upper surface of the mask layer 102 and the interior surface of the deep trench 104 are covered.
As shown in FIG. 1D, an anisotropic etching is conducted to remove the collar oxide layer 114 above the mask layer 102 and the conductive layer 110a and expose the conductive layer 110a. Thereafter, a conductive layer 116 that completely fills the deep trench 104 is formed so that the conductive layer 110a and the conductive layer 116 are electrically connected. The conductive layer 116 is etched back so that the upper surface of the conductive layer 116 is lower than the upper surface 100a of the substrate 100. The exposed collar oxide layer 114 on the sidewalls near the top of the deep trench 104 is removed. Conductive material is deposited into the deep trench 104 to form a conductive layer 118. The conductive layer 118 and the conductive layer 116 are electrically connected and are also electrically connected to the substrate 100. The conductive layer 110a, the conductive layer 116 and the conductive layer 118 together form the upper electrode of the deep trench capacitor
However, in the aforementioned deep trench capacitor manufacturing process, the presence of the seam 112 in the conductive layer 110 leads to the opening of the seam 112 after the etching back process. Consequently, the collar oxide layer 114 at the bottom of the trench after deposition is thicker than the collar oxide layer 114 above the mask layer 102. Furthermore, a portion of the oxide filling material may leak into the seam 112. Hence, when the collar oxide layer 114 is etched, the collar oxide layer 114 over the mask layer 102 may be completely removed before the collar oxide material 114a above the conductive layer 110a and within the seam 112. The residual collar oxide material 114a between the conductive layer 110a and the conductive layer 116 forms an electrical barrier that may lead to memory cell failure and low product yield.
To remove all residual collar oxide material 114a above the conductive layer 110a and within the seam 112, a prolonged etching is required. However, by extending the etching period, thickness of the collar oxide layer lining the sidewalls of the deep trench may be reduced and other device structures may be damaged due to over-etching.
Accordingly, one object of the present invention is to provide a method of manufacturing a deep trench capacitor capable of removing residual collar oxide material from a seam and preventing electrical connectivity problem between a first conductive layer and a second conductive layer within the deep trench. Ultimately, failure of single cells is reduced and product yield of semiconductor devices is improved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of manufacturing a deep trench capacitor. A substrate having a patterned mask layer thereon and a deep trench therein is provided. A doped region is formed in the substrate around the bottom of the deep trench. A conformal capacitor dielectric layer and a first conductive layer are sequentially formed completely filling the deep trench. Due to miniaturization, the deep trench has a high aspect ratio. Hence, a seam is formed in the first conductive layer within the deep trench after conductive material is deposited into the trench. Thereafter, a portion of the first conductive layer is removed to open up the seam. A conformal collar oxide layer and a collar liner are formed over the substrate. Material forming the collar liner layer and material forming the collar oxide layer both have a high etching selectivity ratio. A portion of the collar liner layer is removed so that the collar liner layer on the sidewalls of the deep trench is retained. The collar oxide layer above the mask layer and the first conductive layer is removed. Using the collar liner layer on the sidewalls of the deep trench as a mask, the residual collar oxide layer above the first conductive layer and within the seam is removed. The collar liner layer on the sidewalls of the deep trench is subsequently removed. Finally, a second conductive layer and a second conductive layer are sequentially formed filling the deep trench.
In this invention, a collar liner layer is formed over the collar oxide layer on the interior sidewalls of the deep trench. Hence, the collar liner layer having a lower etching rate than the oxide material can serve as a protective layer for removing any residual oxide layer at the upper surface of the first conductive layer. With the protective collar liner layer, the collar oxide layer can have a constant thickness after an etching operation.
Furthermore, since the collar liner layer can protect the collar oxide layer on the sidewalls of the deep trench, over-etching is less damaging. Hence, extended etching for completely removing any residual collar oxide material above the first conductive layer and within the seam is possible. Without any residual collar oxide material serving as an electrical barrier, memory cell failure is reduced and product yield is increased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.